The present disclosure relates to a phase locked loop circuit that synchronizes a phase, a phase locked loop module having such a phase locked loop circuit, and a phase locked loop method used for such a phase locked loop circuit.
For example, a phase locked loop (PLL) circuit may be configured of a phase comparison circuit, a loop filter, an oscillation circuit, and a frequency divider circuit. In this configuration, for example, the phase comparison circuit may detect a phase difference between a first clock signal supplied from outside and a second clock signal supplied from the frequency divider circuit, and may supply a signal based on the phase difference to the loop filter. The loop filter filters the signal supplied from the phase comparison circuit, the oscillation circuit generates a third clock signal having a frequency corresponding to the filtered signal (for example, voltage), and the frequency divider circuit divides a frequency of the third clock signal, and generates the second clock signal having a frequency being 1/N of the frequency of the third clock signal. In such operation, when a phase of the second clock signal is delayed from a phase of the first clock signal, the phase locked loop circuit controls the phase of the second clock signal to be advanced. When the phase of the second clock signal is advanced from a phase of the first clock signal, the phase locked loop circuit controls the phase of the second clock signal to be delayed. Through such a negative feedback operation, the phase locked loop circuit synchronizes the first clock signal with the second clock signal to generate the third clock signal having a frequency N times higher than the frequency of the first clock signal.
For example, the loop filter may be used for determining response characteristics of the phase locked loop circuit, securing stability, and reducing phase noise. Specifically, it is possible to alter the characteristics of the phase locked loop circuit by altering a filter coefficient of the loop filter. For example, Japanese Unexamined Patent Application Publication No. H10-178343 discloses a phase locked loop circuit having a plurality of loop filters, which is configured to be variable in its characteristics through selection of one of the plurality of loop filters.